Name
Abstract | ||
|---|---|---|
We present new approach to optimize circuits for dynamic reconfiguration in FPGAs. Within a High Level Synthesis tool we optimize the binding of operations to resources to achieve high re-use of resources and interconnect between different configurations. We demonstrate that reconfiguration costs can be drastically reduced, while adding a small area overhead. Moreover our method can merge several tasks into area efficient, static implementations. Both methods allow us to find new trade-offs between resource requirements and reconfiguration costs in dynamic application scenarios. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/FPT.2008.4762397 | FPT |
Keywords | Field | DocType |
field programmable gate arrays,reconfigurable architectures,FPGA,dynamic application scenarios,high level synthesis tool,reconfigurable computing,reconfigurable datapaths synthesis,reconfiguration costs | Resource management,Computer architecture,Computer science,Parallel computing,High-level synthesis,Field-programmable gate array,Implementation,Real-time computing,Electronic circuit,Interconnection,Control reconfiguration,Reconfigurable computing | Conference |
Citations | PageRank | References |
3 | 0.48 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Markus Rullmann | 1 | 27 | 3.82 |
| Renate Merker | 2 | 159 | 20.59 |