| A cost model for partial dynamic reconfiguration | 8 | 0.68 | 2011 |
| An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs | 3 | 0.43 | 2009 |
| Fine grain reconfigurable architectures | 0 | 0.34 | 2008 |
| Synthesis of efficiently reconfigurable datapaths for reconfigurable computing. | 3 | 0.48 | 2008 |
| Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism | 0 | 0.34 | 2008 |
| A Reconfiguration Aware Circuit Mapper for FPGAs | 5 | 0.44 | 2007 |
| Massively Parallel Processor Architectures: A Co-design Approach | 1 | 0.36 | 2007 |
| Maximum edge matching for reconfigurable computing | 5 | 0.55 | 2006 |
| Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels | 0 | 0.34 | 2006 |
| Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy | 2 | 0.39 | 2006 |
| Derivation of Packing Instructions for Exploiting Sub-Word Parallelism | 2 | 0.38 | 2006 |
| Efficient realization of data dependencies in algorithm partitioning under resource constraints | 0 | 0.34 | 2006 |
| Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead | 1 | 0.39 | 2006 |
| An Architecture Description Language for Massively Parallel Processor Architectures. | 5 | 0.53 | 2006 |
| Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching | 5 | 0.60 | 2005 |
| Co-Design of Massively Parallel Embedded Processor Architectures | 9 | 0.67 | 2005 |
| A Parallel Hardware-Software System for Signal Processing Algorithms | 0 | 0.34 | 2004 |
| Optimal loop scheduling with register constraints using flow graphs | 6 | 0.51 | 2004 |
| Optimized Data-Reuse in Processor Arrays | 6 | 0.57 | 2004 |
| Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays | 6 | 0.55 | 2004 |
| Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling | 2 | 0.38 | 2004 |
| A Hardware-Software System for Tomographic Reconstruction | 2 | 0.67 | 2003 |
| Causality Constraints for Processor Architectures with Sub-Word Parallelism | 2 | 0.39 | 2003 |
| Systematic Design of Programs with Sub-Word Parallelism | 5 | 0.50 | 2002 |
| Design of Processor Arrays for Reconfigurable Architectures | 4 | 0.48 | 2001 |
| Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel | 1 | 0.38 | 2000 |
| COMBINING BACKGROUND MEMORY MANAGEMENT AND REGULAR ARRAY CO-PARTITIONING, ILLUSTRATED ON A FULL MOTION ESTIMATION KERNEL | 2 | 0.41 | 2000 |
| Application of Partitioning Methods for the Design of Parallel Programs for a System of Digital Signal Processors | 0 | 0.34 | 2000 |
| High-Level Synthesis System (HLDESA) for Processor Arrays | 2 | 0.39 | 2000 |
| Parallel Processor Array for Tomographic Reconstruction Algorithms | 1 | 0.40 | 1999 |
| Parallelization of algorithms for a system of digital signal processors | 2 | 0.47 | 1999 |
| Localization of Data Transfer in Processor Arrays | 4 | 0.45 | 1999 |
| Hierarchical algorithm partitioning at system level for an improved utilization of memory structures | 33 | 2.30 | 1999 |
| Determination of processor allocation in the design of processor arrays | 8 | 0.69 | 1998 |
| Design of Processor Arrays for Real-Time Applications | 8 | 0.64 | 1998 |
| Determination of the Processor Functionality in the Design of Processor Arrays | 6 | 0.59 | 1997 |
| A System for Designing Parallel Processor Arrays | 5 | 0.55 | 1997 |
| Scheduling in Co-Partitioned Array Architectures | 3 | 0.55 | 1997 |
| Optimization of the background memory utilization by partitioning | 0 | 0.34 | 1997 |
| Propagation of I/O-Variables in Massively Parallel Processor Arrays | 2 | 0.46 | 1996 |
