Name
Abstract | ||
|---|---|---|
When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the serial shifting procedure. In the literature, different scan modification possibilities have been proposed for applying delay fault oriented deterministic test patterns. Another issue to the delay fault testing problem in scan-based sequential circuits is presented in this paper. The solution combines a BIST structure with the standard scan design. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ATS.1998.741653 | Asian Test Symposium |
Keywords | Field | DocType |
automatic test pattern generation,built-in self test,delays,digital integrated circuits,integrated circuit testing,integrated logic circuits,logic testing,sequential circuits,BIST structure,dedicated consecutive two-pattern tests,delay fault testing,deterministic test patterns,scan environment,scan-based sequential circuits,standard scan design | Boundary scan,Stuck-at fault,Automatic test pattern generation,Fault coverage,Computer science,Automatic test equipment,Scan chain,Real-time computing,Electronic engineering,Test compression,Asynchronous circuit | Conference |
ISBN | Citations | PageRank |
0-8186-8277-9 | 3 | 0.47 |
References | Authors | |
22 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Girard | 1 | 478 | 41.91 |
| C. Landrault | 2 | 3 | 0.47 |
| V. Moreda | 3 | 38 | 2.10 |
| S. Pravossoudovitch | 4 | 689 | 54.12 |
| A. Virazel | 5 | 169 | 23.25 |