Name
Abstract | ||
|---|---|---|
Fault diagnosis of Integrated Circuits (ICs) has grown into a special field of interest in the Semiconductor Industry. Fault diagnosis is very useful at the design stage for debugging purposes, at high-volume manufacturing for obtaining feedback about the underlying fault mechanisms and improving the design and layout in future IC generations, and in cases where the IC is part of a larger safety-critical system (e.g. automotive, aerospace) for identifying the root-cause of failure and for applying corrective actions that will prevent failure reoccurrence and, thereby, will expand the safety features. In this summary paper, we present a methodology for fault modeling and fault diagnosis of analog circuits based on machine learning. A defect filter is used to recognize the type of fault (parametric or catastrophic), inverse regression functions are used to locate and predict the values of parametric faults, and multi-class classifiers are used to list catastrophic faults according to their likelihood of occurrence. The methodology is demonstrated on both simulation and high-volume manufacturing data showing excellent overall diagnosis rate. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TEST.2013.6651886 | ITC |
Keywords | Field | DocType |
high-volume manufacturing data,inverse regression functions,ic design,integrated circuit reliability,multiclass classifiers,integrated circuits,analogue integrated circuits,learning (artificial intelligence),circuit analysis computing,regression analysis,pattern classification,defect filter,fault mechanisms,failure analysis,fault diagnosis,catastrophic faults,filters,parametric fault location,integrated circuit layout,ic layout,machine learning,fault modeling,nanometric analog circuits,nanoelectronics,safety-critical system,semiconductor industry,learning artificial intelligence | Stuck-at fault,Integrated circuit layout,Fault coverage,Computer science,Circuit extraction,Real-time computing,Electronic engineering,Parametric statistics,Physical design,Reliability engineering,Debugging,Fault indicator | Conference |
ISSN | Citations | PageRank |
1089-3539 | 0 | 0.34 |
References | Authors | |
12 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ke Huang | 1 | 784 | 67.19 |
| Haralampos-G. D. Stratigopoulos | 2 | 252 | 28.06 |
| Salvador Mir | 3 | 426 | 56.22 |