Paper Info
Title
A multicycle communication architecture and synthesis flow for global interconnect resource sharing
Abstract
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distributed register (DR) architecture to cope with this increasing latency. The DR architecture, though allows multicycle communication, introduces extra overhead on interconnect resource. In this paper, we propose the Regular Distributed Register - Global Resource Sharing (RDR-GRS) architecture to enable global sharing of interconnects and registers. Based on the RDR-GRS architecture, we further define the channel and register allocation problem as a path scheduling problem of data transfers. A formal and flexible formulation of this problem is then presented and optimally solved by Integer Linear Programming (ILP). Experimental results show that RDR-GRS/ILP can averagely reduce 58% wires and 35% registers compared to the previous work.
Year
DOI
Venue
2008
10.1109/ASPDAC.2008.4483933
ASP-DAC
Keywords
Field
DocType
register allocation problem,deep submicron technology,path scheduling problem,global resource,system latency,increasing latency,multicycle communication architecture,rdr-grs architecture,dr architecture,synthesis flow,resource sharing,data transfer,integer linear programming,chromium,logic design,register allocation,fabrication,channel allocation,inductance,shift registers,frequency,resource management,scheduling problem
Resource management,Logic synthesis,Shift register,Job shop scheduling,Register allocation,Computer science,Real-time computing,Electronic engineering,Integer programming,Shared resource,Channel allocation schemes
Conference
ISSN
ISBN
Citations 
2153-6961
978-1-4244-1922-7
5
PageRank 
References 
Authors
0.47
5
4
Name
Order
Citations
PageRank
Wei-Sheng Huang150.47
Yu-Ru Hong2192.32
Juinn-Dar Huang327027.42
Ya-Shih Huang4162.36