Name
Abstract | ||
|---|---|---|
A CMOS voltage reference, based on the difference between the gate-source voltages of two NMOS transistors, has been realized with AMS 0.35 mum CMOS technology (Vthn equiv 0.45 V and Vthn 0.75 V at 0 degC). The minimum and maximum supply voltages are 1.5 V and 4.3 V, respectively. The supply current at the maximum supply voltage and at 80 degC is 2.4 pA. A temperature coefficient of 25 ppm/degC and a line sensitivity of 1.6 mV/V are achieved. The power supply rejection ratios without any filtering capacitor at 100 Hz and 10 MHz are larger than -74 and -59 dB, respectively. The occupied chip area is 0.08 mm2 |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1016/j.mejo.2006.04.011 | Microelectronics Journal |
Keywords | Field | DocType |
power supply rejection ratio,chip,temperature coefficient | Capacitor,NMOS logic,Voltage source,Voltage,Voltage reference,CMOS,Electronic engineering,Engineering,Transistor,Electrical engineering,Low-power electronics | Journal |
Volume | Issue | ISSN |
37 | 10 | Microelectronics Journal |
ISBN | Citations | PageRank |
0-7803-9023-7 | 17 | 3.19 |
References | Authors | |
2 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Giuseppe De Vita | 1 | 34 | 5.69 |
| Giuseppe Iannaccone | 2 | 152 | 24.49 |