Giuseppe Iannaccone

Author Info

Name	Affiliation	Papers
GIUSEPPE IANNACCONE	Department of Information Engineering, University of Pisa-IU.NET, Pisa, Italy	34
Collaborators	Citations	PageRank
70	152	24.49
Referers	Referees	References
476	306	112

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100476

Publications (34 rows)

Collaborators (70 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS	0	0.34	2022
All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification.	0	0.34	2022
Electric-field controlled spin transport in bilayer CrI 3	0	0.34	2021
Electric-field controlled spin transport in bilayer CrI 3	0	0.34	2021
Stability and Startup of Non Linear Loop Circuits.	0	0.34	2019
Variability-aware design of a bandgap voltage reference with 0.18% standard deviation and 68 nW power consumption.	0	0.34	2018
A Portable Class Of 3-Transistor Current References With Low-Power Sub-0.5v Operation	1	0.35	2018
Charge Injection in Normally-Off p-GaN Gate AlGaN/GaN-on-Si HFETs	0	0.34	2018
An Ultralow-Voltage Energy-Efficient Level Shifter.	5	0.56	2017
A 220-mV input, 8.6 step-up voltage conversion ratio, 10.45-μW output power, fully integrated switched-capacitor converter for energy harvesting	0	0.34	2017
Low Energy/Delay Overhead Level Shifter For Wide-Range Voltage Conversion	0	0.34	2017
A sub-1V nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity	0	0.34	2015
A Sub-kT/q Voltage Reference Operating at 150 mV.	0	0.34	2015
Internet-of-things infrastructure as a platform for distributed measurement applications	2	0.39	2015
Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier.	0	0.34	2014
A picopower temperature-compensated, subthreshold CMOS voltage reference.	0	0.34	2014
Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models	1	0.63	2013
Multiscale Modeling for Graphene-Based Nanoscale Transistors	1	0.49	2013
A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation	11	1.73	2013
An intragrid implementation embedded in an Internet of Things platform	1	0.34	2013
Sensitivity-based investigation of threshold voltage variability in 32-nm flash memory cells.	0	0.34	2012
Variability-aware design of 55 nA current reference with 1.4% standard deviation and 290 nW power consumption	1	0.41	2012
CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability	14	0.93	2011
An energy case for hybrid datacenters	61	3.42	2010
Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors	4	1.29	2010
Noise and reliability in simulated thin metal films	0	0.34	2008
Low-voltage nanopower clock generator for RFID applications	3	0.47	2008
CMOS unclonable system for secure authentication based on device variability	9	0.73	2008
A 109 nW, 44 ppm/Â°C CMOS Current Reference with Low Sensitivity to Process Variations	7	1.89	2007
Low-Voltage Low-Power Cmos Oscillator With Low Temperature And Process Sensitivity	13	1.28	2007
Ultra-low-power flash memory in standard 0.35 /spl mu/m CMOS for passive microwave RFID transponders	0	0.34	2006
Ultra-low-power temperature compensated voltage reference generator	17	3.19	2006
Perspectives and challenges in nanoscale device modeling	1	0.63	2005
Ultra low power RF section of a passive microwave RFID transponder in 0.35µm BiCMOS.	0	0.34	2005