Paper Info
Title
Complementary self-biased scheme for the robust design of CMOS/SET hybrid multi-valued logic
Abstract
We propose a new technique to enhance the characteristics of CMOS/SET hybrid multi-valued logic (MVL) circuits in terms of their stability and performance. A complementary self-biasing method enables the SET/CMOS logic to operate perfectly well at high temperature in which the peak-to-valley current ratio of Coulomb oscillation severely decreases. The suggested scheme is evaluated by SPICE simulation with an analytical SET model, and it is confirmed that even SETs with a large Si island can be utilized efficiently in the multi-valued logic. We demonstrate a quantizer implemented by SETs with a 90-nm-long Si island on the basis of measured device characteristics and SPICE simulation, which shows high resolution and small linearity error characteristics.
Year
DOI
Venue
2003
10.1109/ISMVL.2003.1201416
ISMVL
Keywords
Field
DocType
spice simulation,coulomb oscillation,spice,high resolution,ananalytical set model,peak-to-valley current ratio,large si island,set hybrid multi-valued logic,cmos logic,cmos hybrid multivalued logic design,set hybrid multivalued logic design,cmos logic circuits,logic design,multivalued logic circuits,themulti-valued logic,single electron transistors,multivalued logic,robust design,complementary self-biased scheme,measured device characteristic,90-nm-long si island,self-biasing,complementary self-biasing method,temperature,linearity,robustness,semiconductor device modeling,oscillations
Digital electronics,Logic gate,Sequential logic,Pass transistor logic,Computer science,Logic optimization,Electronic engineering,Logic level,Logic family,Integrated injection logic
Conference
ISSN
ISBN
Citations 
0195-623X
0-7695-1918-0
2
PageRank 
References 
Authors
0.45
0
9
Name
Order
Citations
PageRank
Ki-Whan Song1589.66
Sang Hoon Lee28824.05
Dae-Hwan Kim36311.17
Kyung Rok Kim462.33
Jaewoo Kyung520.45
Gwanghyeon Baek620.45
Chun-An Lee720.45
Jong Duk Lee865.16
Byung-Gook Park9714.38