Byung-Gook Park - Citegraph

Author Info

Name	Affiliation	Papers
BYUNG-GOOK PARK	Seoul Natl Univ, Interuniv Semicond Res Ctr ISRC, Seoul 151742, South Korea	40
Collaborators	Citations	PageRank
102	7	14.38
Referers	Referees	References
24	184	49

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100184

Publications (40 rows)

Collaborators (100 rows)

Referers (24 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A Fast Weight Transfer Method for Real-Time Online Learning in RRAM-Based Neuromorphic System	0	0.34	2022
On-Chip Trainable Spiking Neural Networks Using Time-To-First-Spike Encoding	0	0.34	2022
4-bit Multilevel Operation in Overshoot Suppressed Al2O3/TiOx Resistive Random-Access Memory Crossbar Array	0	0.34	2022
Low-Power Adaptive Integrate-and-Fire Neuron Circuit Using Positive Feedback FET Co-Integrated With CMOS	0	0.34	2021
On-Chip Trainable Hardware-Based Deep Q-Networks Approximating A Backpropagation Algorithm	0	0.34	2021
Hardware-based spiking neural network architecture using simplified backpropagation algorithm and homeostasis functionality	0	0.34	2021
Efficient precise weight tuning protocol considering variation of the synaptic devices and target accuracy	0	0.34	2020
Ultrasensitive Electrical Detection of Hemagglutinin for Point-of-Care Detection of Influenza Virus Based on a CMP-NANA Probe and Top-Down Processed Silicon Nanowire Field-Effect Transistors.	0	0.34	2019
Reversible Nonvolatile And Threshold Switching Characteristics In Cu/High-K/Si Devices	0	0.34	2019
Unsupervised Online Learning With Multiple Postsynaptic Neurons Based on Spike-Timing-Dependent Plasticity Using a TFT-Type NOR Flash Memory Array.	0	0.34	2018
Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices.	1	0.35	2017
Bias Polarity Dependent Resistive Switching Behaviors In Silicon Nitride-Based Memory Cell	0	0.34	2016
Resistive Switching Characteristics Of Silicon Nitride-Based Rram Depending On Top Electrode Metals	1	0.48	2015
An Improved Single Image Haze Removal Algorithm Using Image Segmentation.	0	0.34	2014
Vertical Stack Array Of One-Time Programmable Nonvolatile Memory Based On Pn-Junction Diode And Its Operation Scheme For Faster Access	0	0.34	2014
Novel Tunneling Field-Effect Transistor With Sigma-Shape Embedded Sige Sources And Recessed Channel	0	0.34	2013
L-Shaped Tunneling Field-Effect Transistors For Complementary Logic Applications	0	0.34	2013
Study On Threshold Voltage Control Of Tunnel Field-Effect Transistors Using V-T-Control Doping Region	0	0.34	2012
Simulation Study On Scaling Limit Of Silicon Tunneling Field-Effect Transistor Under Tunneling-Predominance	0	0.34	2012
Effects Of Conductive Defects On Unipolar Rram For The Improvement Of Resistive Switching Characteristics	0	0.34	2012
Comparative Study On Top- And Bottom-Source Vertical-Channel Tunnel Field-Effect Transistors	0	0.34	2012
Novel Three Dimensional (3d) Nand Flash Memory Array Having Tied Bit-Line And Ground Select Transistor (Tiger)	0	0.34	2012
A New 1t Dram Cell: Cone Type 1t Dram Cell	0	0.34	2011
The novel SCR-based ESD protection with low triggering and high holding voltages	0	0.34	2011
Simulation Study On Dependence Of Channel Potential Self-Boosting On Device Scale And Doping Concentration In 2-D And 3-D Nand-Type Flash Memory Devices	0	0.34	2010
Simulation Of Gate-All-Around Tunnel Field-Effect Transistor With An N-Doped Layer	0	0.34	2010
Schedulability Analysis On Generalized Quantum-Based Fixed Priority Scheduling	0	0.34	2009
Application Of The Compact Channel Thermal Noise Model Of Short Channel Mosfets To Cmos Rfic Design	0	0.34	2009
Design Consideration For Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (Gibl)	0	0.34	2009
3-Dimensional Terraced Nand (3d Tnand) Flash Memory-Stacked Version Of Folded Nand Array	0	0.34	2009
Simulation Of Retention Characteristics In Double-Gate Structure Multi-Bit Songs Flash Memory	0	0.34	2009
Recessed Channel Dual Gate Single Electron Transistors (Rcdg-Sets) For Room Temperature Operation	0	0.34	2009
Nanosculpture: Three-dimensional CMOS device structures for the ULSI era	0	0.34	2009
Establishing Read Operation Bias Schemes For 3-D Pillar Structure Flash Memory Devices To Overcome Paired Cell Interference (Pci)	3	0.93	2008
Characterization Of 2-Bit Recessed Channel Memory With Lifted-Charge Trapping Node (L-Ctn) Scheme	0	0.34	2008
Design And Simulation Of Asymmetric Mosfets	0	0.34	2007
Analyses On Current Characteristics Of 3-D Mosfet Determined By Junction Doping Profiles For Nonvolatile Memory Devices	0	0.34	2007
Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements	0	0.34	2004
Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers	0	0.34	2003
Complementary self-biased scheme for the robust design of CMOS/SET hybrid multi-valued logic	2	0.45	2003