Name
Abstract | ||
|---|---|---|
A 25 Gb/s × 4-channel transimpedance amplifier has been realized in 65-nm CMOS technology. It achieves transimpedance gain of 69.8 dBΩ, bandwidth of 22.8 GHz, and gains flatness of under ±2 dB after equalizing the effect of transmission loss, incorporating gain-stage amplifier with flat frequency response, and 50Ω-output driver with an analogue equalizer. The proposed TIA dissipates only 74 mW/ch and demonstrates the transimpedance bandwidth products per DC power of 952.1 GHzΩ/mW and crosstalk of less than -17 dB. The sensitivity at bit error rate (BER) of less than 10-12 was measured to be the optical input power of -7.4 dBm for multi-channel operation at the data rate of 25 Gb/s, and also demonstrates only 0.8 dB power penalty. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/CICC.2010.5617420 | CICC |
Keywords | Field | DocType |
cmos analogue integrated circuits,sensitivity,analogue equalizer,bit error rate,transimpedance gain,gain-stage amplifier,size 65 nm,frequency response,channel transimpedance amplifier,operational amplifiers,transmission loss,crosstalk,cmos technology,multichannel operation,dc power,bit rate 25 gbit/s,error statistics,bandwidth 22.8 ghz,flat frequency response,output driver,transimpedance amplifier,gain,cmos integrated circuits,bandwidth | Frequency response,Transmission loss,Computer science,CMOS,Electronic engineering,Bandwidth (signal processing),Transimpedance amplifier,Electrical engineering,Operational amplifier,Amplifier,Bit error rate | Conference |
ISSN | ISBN | Citations |
0886-5930 | 978-1-4244-5758-8 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takashi Takemoto | 1 | 99 | 19.11 |
| Fumio Yuki | 2 | 64 | 10.51 |
| Hiroki Yamashita | 3 | 83 | 14.48 |
| Shinji Tsuji | 4 | 54 | 41.19 |
| Tatsuya Saito | 5 | 38 | 5.32 |
| Shinji Nishimura | 6 | 31 | 5.94 |