Author Info
Name
Affiliation
Papers
HIROKI YAMASHITA
Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo, Japan
16
Collaborators
Citations 
PageRank 
59
83
14.48
Referers 
Referees 
References 
351
179
42
Search Limit
100351
Title
Citations
PageRank
Year
25-Gbps 3-Mw/Gbps/Ch Vcsel Driver Circuit In 65-Nm Cmos For Multichannel Optical Transmitter10.432018
A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology.00.342018
A 50-Gb/S Optical Transmitter Based On A 25-Gb/S-Class Dfb-Ld And A 0.18-Mu M Sige Bicmos Ld Driver00.342016
A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology.00.342016
A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver10.462015
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion90.862014
A 25-to-28 Gb/s High-Sensitivity ( 9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects91.102014
25-Gbps×4 optical transmitter with adjustable asymmetric pre-emphasis in 65-nm CMOS10.382014
High-frequency circuit design for 25 Gb/s×4 optical transceiver.00.342013
A 25-Gb/s × 4-Ch, 8 × 8 mm2, 2.8-mm thick compact optical transceiver module for on-board optical interconnect.20.532013
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS112.452012
A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS00.342010
A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process.373.762010
A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS.00.342009
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane.10.542008
A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface With Digital Eye-Tracking111.932004