Title
Processor Mechanisms for Software Shared Memory
Abstract
The M-Machine's combined hardware-software shared-memory system provides significantly lower remote memory latencies than software DSM systems while retaining the flexibility of software DSM. This system is based around four hardware mechanisms for shared memory: status bits on individual memory blocks, hardware translation of memory addresses to home processors, fast detection of remote accesses, and dedicated thread slots for shared-memory handlers. These mechanisms have been implemented on the MAP processor, and allow remote memory references to be completed in as little as 336 cycles at low hardware cost.
Year
DOI
Venue
2000
10.1007/3-540-39999-2_11
ISHPC
Field
DocType
Volume
Registered memory,Interleaved memory,Uniform memory access,Shared memory,Computer science,Parallel computing,Distributed memory,Memory management,Memory map,Distributed shared memory,Operating system,Embedded system
Conference
1940
ISSN
ISBN
Citations 
0302-9743
3-540-41128-3
2
PageRank 
References 
Authors
0.41
22
5
Name
Order
Citations
PageRank
Nicholas P. Carter134933.84
William J. Dally2117821460.14
Whay Sing Lee3516.68
Stephen W. Keckler43404201.71
Andrew Chang520.41