Name
Title | ||
|---|---|---|
Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches |
Abstract | ||
|---|---|---|
In a multicore processor, different cores typically share the last level cache, and threads running on different cores may interfere with each other in accessing the shared cache. Therefore, multicore WCET (worst case execution time) analyzer must be able to safely and accurately estimate the worst case interthread cache interferences, which is not supported by current WCET analysis techniques that mainly focus on analyzing uniprocessors. This paper proposes a novel approach to analyzing the worst case cache interferences and bounding the WCET for threads running on multicore processors with shared direct mapped L2 instruction caches. We propose to use an extended ILP (integer linear programming) to model all the possible interthread cache conflicts, based on which we can accurately calculate the worst case interthread cache interferences and derive the WCET. Compared to a recently proposed multicore static analysis technique based on control flow information alone, this approach improves the tightness of WCET estimation by 13.7% on average. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/RTCSA.2009.55 | RTCSA |
Keywords | Field | DocType |
wcet analyzer,different core,shared direct-mapped instruction caches,interthread cache interference,multi-core processor,microprocessor chips,wcet estimation,cache storage,possible inter-thread cache conflict,worst-case cache interference,accurately estimating worst-case execution,extended ilp,multicore static analysis technique,worst case execution time accurate estimation,integer programming,multicore processor,l2 instruction cache,direct mapped instruction cache,linear programming,integer linear programming,multi-core processors,last-level cache,control flow information,shared memory systems,current wcet analysis technique,worst-case inter-thread cache interference,shared cache,multicore processing,control flow,multicore processors,real time systems,worst case execution time,static analysis,multi core processor,mathematical model | Worst-case execution time,Cache invalidation,Shared memory,Cache pollution,Computer science,Cache,Parallel computing,Real-time computing,Cache algorithms,Bus sniffing,Smart Cache | Conference |
ISSN | ISBN | Citations |
1533-2306 | 978-0-7695-3787-0 | 20 |
PageRank | References | Authors |
0.95 | 16 | 2 |