Name
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISVLSI.2013.6654635 | ISVLSI |
Keywords | Field | DocType |
integrated circuit design,network routing,power aware computing,system-on-chip,SoC designs,analysis flow,area penalties,body biasing,characterization flow,industrial microprocessor-based design,leakage power reduction,leakage reduction,leakage trade-offs,performance degradation,routing efforts,standard digital design,standard reference supply voltage configuration,system-on-chip designs,timing trade-offs,voltage scaling,Body biasing,leakage reduction,low power,power dissipation,timing analysis,voltage scaling | System on a chip,Leakage (electronics),Propagation delay,Voltage,Electronic engineering,Integrated circuit design,Static timing analysis,Engineering,Threshold voltage,Biasing | Conference |
Citations | PageRank | References |
2 | 0.43 | 5 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andrea Manuzzato | 1 | 7 | 1.34 |
| Fabio Campi | 2 | 227 | 19.26 |
| Davide Rossi | 3 | 416 | 47.47 |
| Valentino Liberali | 4 | 77 | 18.41 |
| Davide Pandini | 5 | 94 | 15.76 |