Davide Pandini - Citegraph

Author Info

Name	Affiliation	Papers
DAVIDE PANDINI	STMicroelectronics, Agrate Brianza, Italy	30
Collaborators	Citations	PageRank
44	94	15.76
Referers	Referees	References
224	435	241

Search Limit

100435

Publications (30 rows)

Collaborators (44 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Design methodology for low-power embedded microprocessors	2	0.41	2013
Evaluating The Impact Of Substrate Noise On Conducted Emi In Automotive Microcontrollers	3	0.86	2013
Exploiting body biasing for leakage reduction: A case study.	2	0.43	2013
Evaluating Static CMOS Complex Cells in Technology Mapping.	0	0.34	2011
SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels.	0	0.34	2011
A design methodology for the automatic sizing of standard-cell libraries	0	0.34	2011
Improving Electro-Magnetic Interference Of Embedded Systems Through Jittered-Delay Desynchronization	0	0.34	2010
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells	1	0.39	2010
EMC-aware design on a microcontroller for automotive applications	3	0.65	2009
Statistical static timing analysis: A survey	11	0.62	2009
Clock-tree synthesis for low-EMI design	0	0.34	2009
Variability in advanced nanometer technologies: challenges and solutions	0	0.34	2009
Computing And Design For Software And Silicon Manufacturing	3	0.43	2007
Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies	1	0.35	2007
Why We Need Statistical Static Timing Analysis	11	0.73	2007
Clock distribution techniques for Low-EMI design	10	0.63	2007
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis	6	0.47	2007
A fully-automated desynchronization flow for synchronous circuits	16	1.14	2007
Power Supply Selective Mapping For Accurate Timing Analysis	0	0.34	2006
Spectral analysis of the on-chip waveforms to generate guidelines for EMC-aware design	5	0.59	2006
Including Power Supply Variations into Static Timing Analysis: Methodology and Flow	3	0.52	2005
Power Supply Selective Mapping for Accurate Timing Analysis	0	0.34	2005
Modeling the non-linear behavior of library cells for an accurate static noise analysis	0	0.34	2005
A complete methodology for an accurate static noise analysis	1	0.37	2005
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures	1	0.36	2004
Design Methodologies and Architecture Solutions for High-Performance Interconnects	2	0.38	2004
Bounding the efforts on congestion optimization for physical synthesis	0	0.34	2003
Understanding and addressing the impact of wiring congestion during technology mapping	5	0.45	2002
Reduced Order Macromodel Of Coupled Interconnects For Timing And Functional Verification Of Sub Half-Micron Ic Designs	0	0.34	1998
Simultaneous placement and module optimization of analog IC's	8	2.27	1994