Name
Abstract | ||
|---|---|---|
A successive approximation register-controlled delay-locked loop (SARDLL) has been fabricated in a 0.25-/spl mu/m standard n-well DPTM CMOS process to realize a fast-lock clock-deskew buffer for long distance clock distribution. This DLL adopts a binary search method to shorten lock time while maintaining tight synchronization between input and output clocks. The measured lock time of the proposed SARDLL is within 30 clock cycles at 100-MWz clock input. The power dissipation is 3.3 mW (not including off-chip driver's) at a 1.1-V supply voltage while the measured rms and peak-to-peak jitter are 11.3 ps and 95 /spl mu/s, respectively. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/4.859501 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
clock distribution,cmos integrated circuits,clock deskew buffer circuit,0.25 micron,3.3 mw,low-power electronics,clocks,lock time,synchronization,successive approximation register controlled delay locked loop,buffer circuits,1.1 v,binary search method,delay lock loops,cmos chip,100 mhz,low power electronics,delay lock loop | Journal | 35 |
Issue | ISSN | Citations |
8 | 0018-9200 | 39 |
PageRank | References | Authors |
4.42 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guang-Kaai Dehng | 1 | 87 | 17.17 |
| June-Ming Hsu | 2 | 71 | 12.17 |
| Ching-Yuan Yang | 3 | 227 | 36.15 |
| Shen-Iuan Liu | 4 | 1378 | 200.41 |