Name
Abstract | ||
|---|---|---|
The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, ... |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/IOLTS.2008.46 | IOLTS |
Keywords | Field | DocType |
low coverage,logic bist,test set,periodic testing,open defect,sensitizable paths,transistors,indexes,netlist,boolean functions,monte carlo methods,merging,data structures,couplings,computational modeling,combinational logic,packaging,redundancy,algorithm design and analysis,testing,accuracy,robustness,attenuation,logic circuits,pipelines,binary decision diagram,logic gates,noise,semiconductor devices,combinational circuits,logic simulation,integrated circuits,upper bound | Boolean function,Netlist,Logic gate,Computer science,Binary decision diagram,Algorithm,Combinational logic,Robustness (computer science),Electronic engineering,Logic simulation,Integrated circuit | Conference |
ISSN | Citations | PageRank |
1942-9398 | 3 | 0.57 |
References | Authors | |
14 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sreenivas Gangadhar | 1 | 18 | 3.50 |
| Michael N. Skoufis | 2 | 8 | 2.34 |
| Spyros Tragoudas | 3 | 625 | 88.87 |