Paper Info
Title
An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization
Abstract
This paper describes TANOR, an automated framework for designing hardware accelerators for numerical computation on reconfigurable platforms. Applications utilizing numerical algorithms on large-size data sets require high-throughput computation platforms. The focus is on N-body interaction problems which have a wide range of applications spanning from astrophysics to molecular dynamics. The TANOR design flow starts with a MATLAB description of a particular interaction function, its parameters, and certain architectural constraints specified through a graphical user interface. Subsequently, TANOR automatically generates a configuration bitstream for a target FPGA along with associated drivers and control software necessary to direct the application from a host PC. Architectural exploration is facilitated through support for fully custom fixed-point and floating-point representations in addition to standard number representations such as single-precision floating point. Moreover, TANOR enables joint exploration of algorithmic and architectural variations in realizing efficient hardware accelerators. TANOR's capabilities have been demonstrated for three different N-body interaction applications: the calculation of gravitational potential in astrophysics, the diffusion or convolution with Gaussian kernel common in image processing applications, and the force calculation with vector-valued kernel function in molecular dynamics simulation. Experimental results show that TANOR-generated hardware accelerators achieve lower resource utilization without compromising numerical accuracy, in comparison to other existing custom accelerators.
Year
DOI
Venue
2009
10.1109/TC.2009.78
IEEE Trans. Computers
Keywords
Field
DocType
drivers,n-body interaction problem,numerical accuracy,reconfigurable hardware,automated framework,high-throughput computation platforms,architectural optimization,asic,tanor design flow,signal processing systems,reconfigurable platforms,different n-body interaction application,image processing applications,molecular dynamics simulation,host pc,algorithms implemented in hardware,reconfigurable architectures,architectural exploration,hardware accelerators,floating-point representations,field- programmable gate arrays,certain architectural constraint,numerical algorithms,numerical algorithms.,algorithmic-architectural optimization,n-body interaction problems,architectural variation,mathematics computing,application specific integrated circuits,custom fixed-point,tanor-generated hardware accelerator,control software,graphical user interface,logic design,fpga,with gaussian kernel,single-precision floating point,vector-valued kernel function,efficient hardware accelerator,field programmable gate arrays,hardware accelerator,matlab description,accelerating numerical algorithms,accuracy,signal processing,hardware,single precision floating point,kernel function,fixed point,kernel,gaussian kernel,design flow,molecular dynamic,resource utilization,floating point,algorithm design and analysis,image processing,graphic user interface
Single-precision floating-point format,MATLAB,Computer science,Floating point,Parallel computing,Algorithm,Field-programmable gate array,Design flow,Graphical user interface,Reconfigurable computing,Kernel (statistics)
Journal
Volume
Issue
ISSN
58
12
0018-9340
Citations 
PageRank 
References 
4
0.51
21
Authors
10
Name
Order
Citations
PageRank
Jung Sub Kim140.84
Lanping Deng2685.91
Prasanth Mangalagiri314711.37
Kevin Irick418018.36
Kanwaldeep Sobti540.51
Mahmut T. Kandemir67371568.54
Narayanan Vijaykrishnan76955524.60
Chaitali Chakrabarti81978184.17
Nikos Pitsianis9396.03
Xiaobai Sun1035139.49