Name
Abstract | ||
|---|---|---|
This paper addresses the problem of simulating gate delay faults in synchronous sequential circuits and presents the solution implemented in the fault simulator DFSIM. In sequential circuits, the fault simulation problem is mainly the propagation of the fault effects through the flip-flops. As different fault sizes may result in different faulty circuit behaviors, to deal with the size of faults during fault propagation is required to provide exact and accurate results. However, due to the high computational complexity, it is not possible to divide fault sizes into fine-grained ranges and simulate each of them separately. In this paper, we propose a method for simulating gate delay faults in sequential circuits which is capable to deal with the size of faults. The solution to the fault simulation problem is obtained by handling the fault size implicitly, rather than explicitly, through a detection range calculation process. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/EDTC.1996.494160 | ED&TC |
Field | DocType | ISSN |
Stuck-at fault,Fault coverage,Propagation delay,Fault detection and isolation,Computer science,Electronic engineering,Real-time computing,Fault (power engineering),Fault Simulator,Fault model,Fault indicator | Conference | 1066-1409 |
ISBN | Citations | PageRank |
0-8186-7423-7 | 1 | 0.39 |
References | Authors | |
17 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Cavallera | 1 | 1 | 0.39 |
| P. Girard | 2 | 478 | 41.91 |
| C. Landrault | 3 | 1 | 0.39 |
| S. Pravossoudovitch | 4 | 689 | 54.12 |