Name
Abstract | ||
|---|---|---|
The design process of an 8-bit 32-processing-units serial pipeline VLSI modular processor performing the parallel execution of a kernel classifier recall phase is described. Starting from VHDL high-level modelling, after verifying the correct circuit behaviour by means of digital simulation, the circuit has been synthesized and mapped on a 0.7 micron CMOS technology. Both area and delay optimized syntheses are performed for each processor cell, selecting in each case the best solution. Taking advantage of the constant data flow of the pipeline architecture, a dynamic realization of the memory elements using tri-state standard cells is proposed. This reduces both the circuit area and delays, without losing the convenience of an automatic standard cell placement and routing. From synthesis results, a working frequency of about 300 MHz is expected. A parallel-serial interface reduces external clock frequency requirements, and thus matching the external frequency limitations with fast on-chip processing. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1007/BFb0032539 | IWANN |
Keywords | Field | DocType |
bit-serial pipeline kernel processor,data flow,design process,chip | Computer science,Parallel computing,CMOS,Standard cell,Modular design,VHDL,Very-large-scale integration,Clock rate,Data flow diagram,Kernel (statistics) | Conference |
Volume | ISSN | ISBN |
1240 | 0302-9743 | 3-540-63047-3 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jordi Madrenas | 1 | 150 | 27.87 |
| Gregorio Ruiz | 2 | 0 | 0.34 |
| Juan Manuel Moreno | 3 | 186 | 32.74 |
| joan cabestany | 4 | 1276 | 143.82 |