| A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation | 0 | 0.34 | 2022 |
| A CMOS-MEMS BEOL 2-axis Lorentz-Force Magnetometer with Device-Level Offset Cancellation. | 0 | 0.34 | 2020 |
| A test setup for the characterization of Lorentz-force MEMS magnetometers | 0 | 0.34 | 2020 |
| Resonant MEMS Pressure Sensor in 180 nm CMOS Technology Obtained by BEOL Isotropic Etching. | 0 | 0.34 | 2020 |
| LEGION-based image segmentation by means of spiking neural networks using normalized synaptic weights implemented on a compact scalable neuromorphic architecture. | 0 | 0.34 | 2019 |
| Axonal Delay Controller for Spiking Neural Networks Based on FPGA | 0 | 0.34 | 2019 |
| Efficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus. | 0 | 0.34 | 2018 |
| Experiments on MEMS Integration in 0.25 μm CMOS Process. | 1 | 0.48 | 2018 |
| Optimizing Power Consumption vs. Linearization in CMFB Amplifiers with Source Degeneration | 1 | 0.39 | 2018 |
| SNAVA-A real-time multi-FPGA multi-model spiking neural network simulation architecture. | 1 | 0.35 | 2018 |
| Self-adaptive hardware architecture with parallel processing capabilities and dynamic reconfiguration | 0 | 0.34 | 2017 |
| Cmos Majority Circuit With Large Fan-In | 0 | 0.34 | 2016 |
| Integration of GMR Sensors with Different Technologies. | 5 | 0.73 | 2016 |
| AER-SRT: Scalable spike distribution by means of synchronous serial ring topology address event representation | 7 | 0.79 | 2016 |
| Synfire Chain Emulation By Means Of Flexible Snn Modeling On A Simd Multicore Architecture | 0 | 0.34 | 2016 |
| Compact Associative Memory For Aer Spike Decoding In Fpga-Based Evolvable Snn Emulation | 0 | 0.34 | 2016 |
| u-Help: supporting helpful communities with information technology | 0 | 0.34 | 2013 |
| A Novel Alternative Exponent-Weighted Fuzzy C-Means Algorithm | 0 | 0.34 | 2013 |
| Pulsed Digital Oscillators for Electrostatic MEMS. | 0 | 0.34 | 2012 |
| A Translinear, Log-Domain FPAA on Standard CMOS Technology. | 10 | 0.73 | 2012 |
| Continuous-time CMOS adaptive asynchronous ΣΔ modulator approximating low-ƒs low-inband-error on-chip wideband power amplifier | 1 | 0.37 | 2011 |
| Bioinspired Sensory Integration for Environment-Perception Embedded Systems. | 1 | 0.36 | 2011 |
| A self-test and dynamics characterization circuit for MEMS electrostatic actuators | 1 | 0.40 | 2011 |
| Implementation of a power-aware dynamic fault tolerant mechanism on the Ubichip platform | 1 | 0.35 | 2010 |
| Performance evaluation and scaling of a multiprocessor architecture emulating complex SNN algorithms | 0 | 0.34 | 2010 |
| Experiments on the Release of CMOS-Micromachined Metal Layers | 4 | 0.91 | 2010 |
| A low-voltage current sorting circuit based on 4-T min-max CMOS switch. | 4 | 0.48 | 2010 |
| Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware Architecture | 5 | 0.54 | 2009 |
| Synchronous Digital Implementation of the AER Communication Scheme for Emulating Large-Scale Spiking Neural Networks Models | 1 | 0.43 | 2009 |
| Translinear signal processing circuits in standard CMOS FPAA | 0 | 0.34 | 2009 |
| Strategies in SIMD Computing for Complex Neural Bioinspired Applications | 2 | 0.47 | 2009 |
| SpiNDeK: an integrated design tool for the multiprocessor emulation of complex bioinspired spiking neural networks | 4 | 0.50 | 2009 |
| A reconfigurable architecture for emulating large-scale bio-inspired systems | 6 | 0.53 | 2009 |
| A reconfigurable translinear cell architecture for CMOS field-programmable analog arrays | 1 | 0.43 | 2008 |
| The PERPLEXUS bio-inspired hardware platform: A flexible and modular approach | 6 | 0.74 | 2008 |
| A MOSFET-Based Wide-Dynamic-Range Translinear Element | 1 | 0.43 | 2008 |
| BAF: A Bio-Inspired Agent Framework for Distributed Pervasive Applications | 0 | 0.34 | 2008 |
| The Perplexus bio-inspired reconfigurable circuit | 29 | 1.88 | 2007 |
| A Novel Hardware Architecture for Self-adaptive Systems | 4 | 0.49 | 2007 |
| Design and basic blocks of a neuromorphic VLSI analogue vision system | 4 | 0.41 | 2006 |
| Evolvable Systems: From Biology to Hardware, 6th International Conference, ICES 2005, Sitges, Spain, September 12-14, 2005, Proceedings | 21 | 2.30 | 2005 |
| Selective similarity function for VLSI analog signal processing | 1 | 0.42 | 2005 |
| BIOSEG: a bioinspired vlsi analog system for image segmentation | 2 | 0.49 | 2004 |
| A microelectronic implementation of a bioinspired analog matrix for object segmentation of a visual scene | 0 | 0.34 | 2001 |
| Feasible Evolutionary and Self-Repairing Hardware by Means of the Dynamic Reconfiguration Capabilities of the FIPSOC Devices | 6 | 0.76 | 1998 |
| Improving the Performance of Piecewise Linear Separation Incremental Algorithms for Practical Hardware Implementations | 0 | 0.34 | 1997 |
| Using Classical and Evolutive Neural Models in Industrial Applications: A Case Study for an Automatic Coin Classifier | 2 | 0.41 | 1997 |
| Synthesis and Optimization of a Bit-Serial Pipeline Kernel Processor | 0 | 0.34 | 1997 |
| Analog Sequential Architecture for Neuro-Fuzzy Models VLSI Implementation | 1 | 0.40 | 1997 |
| A deterministic method for establishing the initial conditions in the RCE algorithm. | 0 | 0.34 | 1995 |
