Name
Title | ||
|---|---|---|
Cross-layer power management in wireless networks and consequences on system-level architecture |
Abstract | ||
|---|---|---|
Low power consumption is imperative to enable the deployment of broadband wireless connectivity in portable devices such as PDA's or smart phones. Next to low power circuit and architecture design, system-level power management reveals to be a key technology for low power consumption. Recently, "lazy scheduling" has been proposed for system level power reduction. It has been shown to be very effective and complementary to more traditional shutdown-based approaches. So far, analysis has been carried out from the viewpoint of medium access control (MAC) and data link control (DLC) layers. Yet, effective power management in radio communication requires considering end-to-end cross-layer interactions. In this paper, we analyze the implication of lazy scheduling from the end-to-end perspective, considering the interaction with the transport layer. It is shown that a key tradeoff between queuing delay and physical layer energy drives the transport-level tradeoff between user throughput and system power. Conditions under which lazy scheduling is efficient are established. Further, it is shown that the user throughput vs. system power tradeoff can be controlled by adapting the lazy scheduling policy. Finally, important conclusions on effective system-level architecture and cross-layer power management are drawn. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1016/j.sigpro.2005.09.035 | Signal Processing |
Keywords | Field | DocType |
system power,cross-layer power management,wireless network,system power tradeoff,low power consumption,system level power reduction,system-level power management,low power circuit,user throughput,system-level architecture,effective power management,lazy scheduling,data link control,physical layer,wireless networks,transport layer | Wireless network,Power management,Mathematical optimization,Wireless broadband,Scheduling (computing),Queuing delay,Computer network,Physical layer,Systems architecture,Throughput,Mathematics,Embedded system | Journal |
Volume | Issue | ISSN |
86 | 8 | Signal Processing |
Citations | PageRank | References |
7 | 1.29 | 17 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bruno Bougard | 1 | 593 | 57.27 |
| Sofie Pollin | 2 | 1041 | 113.94 |
| Antoine Dejonghe | 3 | 309 | 30.25 |
| Francky Catthoor | 4 | 3932 | 423.30 |
| Wim Dehaene | 5 | 874 | 116.42 |