| Efficient Backside Power Delivery for High-Performance Computing Systems | 0 | 0.34 | 2022 |
| Fail-Safe Human Detection for Drones Using a Multi-Modal Curriculum Learning Approach | 0 | 0.34 | 2022 |
| A Survey on Memory-centric Computer Architectures | 0 | 0.34 | 2022 |
| VWR2A: a very-wide-register reconfigurable-array architecture for low-power embedded devices | 0 | 0.34 | 2022 |
| CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out | 1 | 0.35 | 2022 |
| Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices | 0 | 0.34 | 2022 |
| Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow | 0 | 0.34 | 2021 |
| Dynamic Reliability Management in Neuromorphic Computing | 0 | 0.34 | 2021 |
| Low-Power Memristor-Based Computing For Edge-Ai Applications | 0 | 0.34 | 2021 |
| Fast And Accurate Edge Computing Energy Modeling And Dvfs Implementation In Gem5 Using System Call Emulation Mode | 0 | 0.34 | 2021 |
| A Retargetable MATLAB-to-C Compiler Exploiting Custom Instructions and Data Parallelism | 0 | 0.34 | 2020 |
| Cardiac Comorbidities in COPD Patients Explained Through HRV and Respiratory Indices | 0 | 0.34 | 2020 |
| A Synergy of a Closed-Loop DVFS Controller and CPU Hot-Plug For Run-Time Thermal Management in Multicore Systems | 0 | 0.34 | 2019 |
| Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects | 0 | 0.34 | 2019 |
| A Closed-Loop Controller to Ensure Performance and Temperature Constraints for Dynamic Applications. | 0 | 0.34 | 2019 |
| Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM | 1 | 0.37 | 2019 |
| Impact and mitigation of SRAM read path aging. | 0 | 0.34 | 2018 |
| Graceful Performance Adaption through Hardware-Software Interaction for Autonomous Battery Management of Multicore Smartphones | 0 | 0.34 | 2018 |
| Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier. | 7 | 0.62 | 2017 |
| Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures. | 0 | 0.34 | 2016 |
| Tackling Performance Variability due to RAS Mechanisms with PID-Controlled DVFS | 7 | 0.48 | 2015 |
| Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems. | 1 | 0.35 | 2015 |
| HARPA: Solutions for dependable performance under physically induced performance variability | 2 | 0.39 | 2015 |
| Integral impact of BTI and voltage temperature variation on SRAM sense amplifier | 5 | 0.51 | 2015 |
| BTI analysis of SRAM write driver | 2 | 0.40 | 2015 |
| Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node | 0 | 0.34 | 2015 |
| Worst-Case Throughput Analysis For Parametric Rate And Parametric Actor Execution Time Scenario-Aware Dataflow Graphs | 8 | 0.49 | 2014 |
| Exploration of energy efficient memory organisations for dynamic multimedia applications using system scenarios | 5 | 0.53 | 2013 |
| Early exploration for platform architecture instantiation with multi-mode application partitioning | 1 | 0.37 | 2013 |
| A systematic approach to classify design-time global scheduling techniques | 4 | 0.39 | 2013 |
| IMOSIM: Exploration tool for Instruction Memory Organisations based on accurate cycle-level energy modelling | 1 | 0.39 | 2012 |
| High Level Analysis Of Trade-Offs Across Different Partitioning Schemes For Wireless Applications | 0 | 0.34 | 2011 |
| Automated architecture exploration for low energy reconfigurable AGU | 7 | 1.72 | 2011 |
| Software metadata: Systematic characterization of the memory behaviour of dynamic applications | 9 | 0.68 | 2010 |
| Exploiting finite precision information to guide data-flow mapping | 0 | 0.34 | 2010 |
| Design of fuzzy cognitive maps using neural networks for predicting chaotic time series | 24 | 1.08 | 2010 |
| A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms | 8 | 0.56 | 2010 |
| A spatial learning algorithm for IEEE 802.11 networks | 1 | 0.37 | 2009 |
| Playing the trade-off game: Architecture exploration using Coffeee | 2 | 0.41 | 2009 |
| Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments | 1 | 0.35 | 2009 |
| Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS | 0 | 0.34 | 2009 |
| Energy Aware Algorithm and Implementation of SDR Oriented HSDPA Chip Level Equalizer | 1 | 0.44 | 2009 |
| Interconnect exploration for energy versus performance tradeoffs for coarse grained reconfigurable architectures | 8 | 0.55 | 2009 |
| How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach | 0 | 0.34 | 2008 |
| Semi custom design: a case study on SIMD shufflers | 0 | 0.34 | 2007 |
| Real-Time Stereo Correspondence using a Truncated Separable Laplacian Kernel Approximation on Graphics Hardware | 5 | 0.45 | 2007 |
| SmartMIMO: An Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Next-Generation Wireless Local Area Networks | 1 | 0.35 | 2007 |
| Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy. | 11 | 1.10 | 2007 |
| Software simultaneous multi-threading, a technique to exploit task-level parallelism to improve instruction- and data-level parallelism | 3 | 0.42 | 2006 |
| Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications | 2 | 0.36 | 2006 |
