Name
Abstract | ||
|---|---|---|
The setup and hold timing constraints are two types of timing constraints, which should be kept by each operation, and they may be violated by the timing variation of control signals. In this paper, we show that we can solve such potential timing violations in high-level synthesis without degrading speed performance, but by devising register assignment and clocking scheme. That is, we will combine Backward-Data-Direction (BDD) clocking, Forward-Data-Direction (FDD) clocking, and Structural Robustness against delay Variation (SRV)-based register assignment to solve potential timing violations. First, we formulate the problem as a minimum register assignment problem for datapaths which has a proper ordered clocking. After that, we propose an integer linear programming (ILP) formulation and show the experimental results for some benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1531542.1531553 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
control signal,datapath synthesis,minimum register assignment problem,clocking scheme,safe clocking,benchmark circuit,timing constraint,timing variation,devising register assignment,structural robustness,register assignment,potential timing violation,high level synthesis,assignment problem | Datapath,Computer science,Parallel computing,Real-time computing,Register assignment,Integer programming,Electronic circuit,Structural robustness | Conference |
Citations | PageRank | References |
1 | 0.41 | 9 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keisuke Inoue | 1 | 134 | 17.50 |
| Mineo Kaneko | 2 | 30 | 17.25 |
| Tsuyoshi Iwagaki | 3 | 29 | 8.42 |