Tsuyoshi Iwagaki - Citegraph

Author Info

Name	Affiliation	Papers
TSUYOSHI IWAGAKI	Hiroshima City Univ, Grad Sch Informat Sci, Asaminami Ku, 3-4-1 Ozuka Higashi, Hiroshima 7313194, Japan	22
Collaborators	Citations	PageRank
21	29	8.42
Referers	Referees	References
65	262	172

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100262

Publications (22 rows)

Collaborators (21 rows)

Referers (65 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis	0	0.34	2019
Compact and Accurate Digital Filters Based on Stochastic Computing	6	0.49	2019
State assignment for fault tolerant stochastic computing with linear finite state machines	1	0.38	2017
Designing area-efficient controllers for multi-cycle transient fault tolerant systems	2	0.43	2015
A practical approach for logic simplification based on fault acceptability for error tolerant application	0	0.34	2015
Logic simplification by minterm complement for error tolerant application	3	0.47	2015
A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test	0	0.34	2013
Utilizing Register Transfer Level False Paths For Circuit Optimization With A Logic Synthesis Tool	0	0.34	2012
Flexible Test Scheduling For An Asynchronous On-Chip Interconnect Through Special Data Transfer	0	0.34	2011
Backward-Data-Direction Clocking And Relevant Optimal Register Assignment In Datapath Synthesis	1	0.39	2011
A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties	0	0.34	2010
Optimal Register Assignment With Minimum-Path Delay Compensation For Variation-Aware Datapaths	0	0.34	2009
Safe clocking for the setup and hold timing constraints in datapath synthesis	1	0.41	2009
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation	4	0.47	2008
Safe Clocking Register Assignment In Datapath Synthesis	2	0.42	2008
Efficient path delay test generation based on stuck-at test generation using checker circuitry	0	0.34	2007
Broadside Transition Test Generation For Partial Scan Circuits Through Stuck-At Test Generation	0	0.34	2006
A Low Power Deterministic Test Using Scan Chain Disable Technique	4	0.45	2006
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation	0	0.34	2005
Acceleration of Transition Test Generation for Acyclic Sequential Circuits Utilizing Constrained Combinational Stuck-At Test Generation	3	0.41	2005
A Design Methodology to Realize Delay Testable Controllers Using State Transition Information	1	0.36	2004
Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models	1	0.36	2003