Name
Title | ||
|---|---|---|
Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS |
Abstract | ||
|---|---|---|
The raising cost of the latest technology nodes as well as the design cost associated has motivated an increasing push for flexible radio implementations. In this context, Sigma-Delta (SigmaDelta) ADCs have emerged as a promising alternative to direct conversion. In this work a novel wireless receiver architecture based on an RF bandpass SigmaDelta is considered. One of the key blocks of this architecture is the digital decimation filter which needs to run at very high speed. In order to offer competitive power consumption, the implementation of this decimation filter needs to be thoroughly optimized. Considering that many implementation options are possible, this paper presents an early evaluation flow, which still considers relevant implementation details to aid designers in selecting the most optimal implementation option. The flow is shown for a design of a 9-bits ADC targeting 40 nm CMOS technology. The power consumption of the optimal implementation option is shown to be below 12.6 mW. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/SIPS.2009.5336241 | 2009 IEEE Workshop on Signal Processing Systems |
Keywords | Field | DocType |
Decimation Filters,Sigma Delta ADCs,Wireless Receiver Architecture | Wireless,Digital filter,Decimation,Band-pass filter,Computer science,CMOS,Real-time computing,Electronic engineering,Implementation,Delta-sigma modulation,Finite impulse response,Embedded system | Conference |
ISSN | Citations | PageRank |
2162-3562 | 0 | 0.34 |
References | Authors | |
3 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Novo | 1 | 110 | 12.88 |
| Robert Fasthuber | 2 | 20 | 4.26 |
| Praveen Raghavan | 3 | 308 | 47.48 |
| André Bourdoux | 4 | 274 | 42.21 |
| Min Li | 5 | 160 | 23.21 |
| Liesbet Van Der Perre | 6 | 1013 | 108.24 |
| Francky Catthoor | 7 | 3932 | 423.30 |