Name
Title | ||
|---|---|---|
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level |
Abstract | ||
|---|---|---|
This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it suitable to switching noise evaluation and current peaks localisation. Simulation results and comparison to HSPICE confirm the usefulness and efficiency of the approach. |
Year | Venue | Keywords |
|---|---|---|
2002 | PATMOS | noise evaluation,logic level,simple current model,simulation result,overall estimation,current estimation,attached module,cmos digital circuits,current peaks localisation,fast current curve estimation,logic simulator,current curve generation algorithm,generic algorithm,digital circuits |
Field | DocType | ISBN |
Digital electronics,Spice,Computer science,Waveform,Electronic engineering,CMOS,Logic simulation,Logic level,Estimation theory,Integrated circuit | Conference | 3-540-44143-3 |
Citations | PageRank | References |
1 | 0.38 | 6 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Paulino Ruiz-de-clavijo | 1 | 21 | 6.72 |
| Jorge Juan-chico | 2 | 31 | 6.52 |
| Manuel J. Bellido | 3 | 82 | 11.82 |
| Alejandro Millán | 4 | 10 | 5.77 |
| David Guerrero | 5 | 14 | 5.86 |