| Address-encoded byte order | 0 | 0.34 | 2020 |
| Fast Hardware Implementations of Static P Systems. | 0 | 0.34 | 2016 |
| Long-term on-chip verification of systems with logical events scattered in time | 1 | 0.43 | 2012 |
| Studying The Viability Of Static Complementary Metal-Oxide-Semiconductor Gates With A Large Number Of Inputs When Using Separate Transistor Wells | 0 | 0.34 | 2011 |
| Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation | 0 | 0.34 | 2011 |
| Comprehensive Analysis On The Internal Power Dissipation Of Static Cmos Cells In Ultra-Deep Sub-Micron Technologies | 0 | 0.34 | 2010 |
| Design and implementation of a suitable core for on-chip long-term verification | 0 | 0.34 | 2010 |
| Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates | 0 | 0.34 | 2008 |
| Delay-Assignment-Variation Based Optimization Of Digital Cmos Circuits For Low Power Consumption | 1 | 0.48 | 2007 |
| Static power consumption in CMOS gates using independent bodies | 0 | 0.34 | 2007 |
| Accurate Logic-Level Current Estimation For Digital Cmos Circuits | 0 | 0.34 | 2006 |
| Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements | 1 | 0.48 | 2006 |
| Internode: Internal Node Logic Computational Model | 2 | 0.43 | 2003 |
| Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level | 1 | 0.38 | 2002 |
| Characterization of Normal Propagation Delay for Delay Degradation Model (DDM) | 4 | 0.53 | 2002 |
