A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks.

Paper Info

Title
A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks.

Year	DOI	Venue
2012	10.1007/978-3-642-45073-0_7	VLSI-SoC (Selected Papers)
Field	DocType	Citations
Mesh networking,Baseband,Computer science,Hexagonal tiling,Parallel computing,Network topology,Encoder,Orthogonal frequency-division multiplexing,Microarchitecture,Scalability	Conference	1
PageRank	References	Authors
0.35	12	2

Authors (2 rows)

Cited by (1 rows)

References (12 rows)

Name	Order	Citations	PageRank
Zhibin Xiao	1	22	4.85
Bevan M. Baas	2	295	27.78