Name
Title | ||
|---|---|---|
Reducing cache and TLB power by exploiting memory region and privilege level semantics. |
Abstract | ||
|---|---|---|
The L1 cache in today’s high-performance processors accesses all ways of a selected set in parallel. This constitutes a major source of energy inefficiency: at most one of the N fetched blocks can be useful in an N-way set-associative cache. The other N-1 cachelines will all be tag mismatches and subsequently discarded. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1016/j.sysarc.2013.04.002 | Journal of Systems Architecture |
Keywords | Field | DocType |
First-level cache,Translation lookaside buffer,Memory regions,Ring level,Simulation | Cache invalidation,Cache pollution,Cache,Computer science,MESI protocol,Parallel computing,Page cache,Cache algorithms,Real-time computing,Cache coloring,Smart Cache,Operating system | Journal |
Volume | Issue | ISSN |
59 | 6 | 1383-7621 |
Citations | PageRank | References |
1 | 0.35 | 24 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhen Fang | 1 | 91 | 7.62 |
| Li Zhao | 2 | 604 | 34.84 |
| Xiaowei Jiang | 3 | 43 | 2.25 |
| Shih-Lien Lu | 4 | 958 | 67.34 |
| Ravishankar K. Iyer | 5 | 1119 | 75.72 |
| Tong Li | 6 | 1 | 0.35 |
| Seung Eun Lee | 7 | 224 | 22.34 |