Name
Affiliation
Papers
RAVISHANKAR K. IYER
Center for Reliable and High-Performance Computing|University of Illinois at Urbana-Champaign
72
Collaborators
Citations 
PageRank 
169
1119
75.72
Referers 
Referees 
References 
2521
1398
846
Search Limit
1001000
Title
Citations
PageRank
Year
Cache Compression with Efficient in-SRAM Data Comparison00.342021
RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization00.342020
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks.290.712018
Visual IoT: Ultra-Low-Power Processing Architectures and Implications.40.532017
QoS Management on Heterogeneous Architecture for Multiprogrammed, Parallel, and Domain-Specific Applications.00.342017
Visual IoT: Architectural Challenges and Opportunities; Toward a Self-Learning and Energy-Neutral IoT.10.352016
Design of a low power SoC testchip for wearables and IoTs00.342015
Platform-aware dynamic configuration support for efficient text processing on heterogeneous system00.342015
A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs150.752014
A systematic network-on-chip traffic modeling and generation methodology20.372014
QoS management on heterogeneous architecture for parallel applications20.362014
Moral values from simple game play10.352013
Reducing cache and TLB power by exploiting memory region and privilege level semantics.10.352013
Reducing L1 caches power by exploiting software semantics30.412012
Dynamic QoS management for chip multiprocessors60.412012
Optimizing datacenter power with memory system levers for guaranteed quality-of-service70.432012
Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms100.612011
CogniServe: Heterogeneous Server Architecture for Large-Scale Recognition120.762011
CHOP: Integrating DRAM Caches for CMP Server Platforms230.862011
Template-based memory access engine for accelerators in SoCs50.442011
RAFT: A router architecture with frequency tuning for on-chip networks190.712011
Low-Power, Resilient Interconnection with Orthogonal Latin Squares100.712011
CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs170.582011
NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies60.462010
Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact10.372010
PIRATE: QoS and performance management in CMP architectures120.582010
Rate-based QoS techniques for cache/memory in CMP platforms271.332009
Hardware/Software Co-Simulation for Last Level Cache Exploration00.342009
A case for dynamic frequency tuning in on-chip networks611.752009
Virtual platform architectures for resource metering in datacenters120.612009
Modeling virtual machine performance: challenges and approaches311.462009
Accelerating mobile augmented reality on a handheld platform221.282009
VM3: Measuring, modeling and managing VM shared resources372.182009
Performance characterization and optimization of mobile augmented reality on handheld platforms100.862009
Achieving 10Gbps network processing: are we there yet?20.442008
Towards hybrid last level caches for chip-multiprocessors170.982008
Secure Web-Based Sharing of Health Information Services Using Ad-Hoc Dynamic Coalitions00.342008
Implications of cache asymmetry on server consolidation performance150.912008
Characterization & analysis of a server consolidation benchmark272.042008
Towards modeling & analysis of consolidated CMP servers150.762008
Coalition Service Registry for Ad-hoc Dynamic Coalitions00.342008
qTLB: looking inside the look-aside buffer50.472007
Hardware Support for Accelerating Data Movement in Server Platform120.742007
CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms473.122007
From chaos to QoS: case studies in CMP resource management411.702007
Addressing Cache/Memory Overheads in Enterprise Java CMP Servers40.452007
Exploring Large-Scale CMP Architectures Using ManySim171.172007
I/O processing in a virtualized platform: a simulation-driven approach91.062007
Architectural characterization of VM scaling on an SMP machine10.382006
Receive side coalescing for accelerating TCP/IP processing172.892006
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