Name
Title | ||
|---|---|---|
Using functional independence conditions to optimize the performance of latency-insensitive systems |
Abstract | ||
|---|---|---|
In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamically control their operations. In particular, a shell stalls a pearl whenever new valid data are not available on its input channels. We study how functional independence conditions (FIC) can be applied to the performance optimization of a latency-insensitive system by avoiding unnecessary stalling of their pearls. We present a novel circuit design of a generic shell template that can exploit FICs. We describe an automatic procedure for the logic synthesis of a FIC-shell instance that is only based on the analysis of the logic structure of its corresponding pearl and does not require any input from the designers. We implemented the proposed technique within the logic synthesis tool ABC and we use it to complete various experiments that demonstrate its performance benefits and limited overhead. In particular, we completed the semi-custom design of a system-on-chip (SoC), an ultra-wideband baseband transmitter, using a state-of-the-art 90nm technology process. To the best of our knowledge this represents the first report on the complete latency-insensitive design of a real-world SoC.
|
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ICCAD.2007.4397240 | ICCAD |
Keywords | Field | DocType |
latency-insensitive design shell module,logic structure,system components encapsulation,latency-insensitive system,shell template,circuit optimisation,generic shell template,system-on-chip,latency-insensitive systems,ultra-wideband baseband transmitter,logic design,functional independence condition,functional independence conditions,logic synthesis tool abc,logic synthesis,logic structure analysis,performance optimization,latency-insensitive design shell modules,semi-custom design,novel circuit design,complete latency-insensitive design,latency-insensitive protocol,circuit design,computer science,electromagnetics,simulation,finite element method,ultra wideband,system on chip,modeling,time domain | Time domain,Logic synthesis,Baseband,System on a chip,Computer science,Electromagnetics,Communication channel,Circuit design,Electronic engineering,Real-time computing,Exploit,Embedded system | Conference |
ISSN | ISBN | Citations |
1092-3152 E-ISBN : 978-1-4244-1382-9 | 978-1-4244-1382-9 | 3 |
PageRank | References | Authors |
0.41 | 19 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cheng-Hong Li | 1 | 79 | 5.98 |
| Luca P. Carloni | 2 | 1713 | 120.17 |