Title | ||
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An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators |
Abstract | ||
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A rail-to-rail differential input stage with programmable thresholdlevels and offset compensation is introduced. Applications for theimplementation of differential and double differential comparatorsare discussed. Experimental results obtained from a MOSIS0.5µm CMOS technology test chip are shown that validaterail-to-rail operation with a 1.5V supply voltage. |
Year | DOI | Venue |
---|---|---|
2008 | 10.1109/VLSI.2008.30 | VLSI Design |
Keywords | Field | DocType |
input stage,validaterail-to-rail operation,m cmos technology test,double differential comparatorsare,programmable thresholdlevels,rail-to-rail differential input stage,rail offset compensated cmos,low-voltage rail,supply voltage,chip,low voltage | Comparators circuits,Comparator,Input offset voltage,Computer science,Voltage,Chip,Electronic engineering,CMOS,Low voltage,Electrical engineering,Offset (computer science) | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-7695-3083-4 | 0 |
PageRank | References | Authors |
0.34 | 1 | 8 |
Name | Order | Citations | PageRank |
---|---|---|---|
Jaime Ramírez-Angulo | 1 | 138 | 23.59 |
Lalitha Mohana Kalyani-Garimella | 2 | 0 | 0.34 |
Annajirao Garimella | 3 | 39 | 5.83 |
Sri Raga Sudha Garimella | 4 | 5 | 2.31 |
Antonio Lopez-Martin | 5 | 34 | 9.14 |
Ramón González Carvajal | 6 | 681 | 153.63 |
Ramirez-Angulo, J. | 7 | 0 | 0.34 |
Kalyani-Garimella, L.M. | 8 | 1 | 0.71 |