Paper Info
Title
Design of Reusable VHDL Component Using External Functions.
Abstract
Abstract: This paper presents a method how to represent and build a reusable VHDLcomponent. The representation is based on external functions use. The design procedure is described astransferring of characteristics intrinsic for a given class of domain objects and features from a givenVHDL model by re-coding and extending this model with new features. The formal syntax of thefunctions is given. The component instantiation is performed via pre-processing.
Year
DOI
Venue
1998
10.3233/INF-1998-9409
Informatica, Lith. Acad. Sci.
Field
DocType
Volume
Computer architecture,Programming language,Computer science,Artificial intelligence,Formal grammar,VHDL,User interface,Semantics,Machine learning
Journal
9
Issue
Citations 
PageRank 
4
2
0.40
References 
Authors
10
1
Name
Order
Citations
PageRank
Vytautas Stuikys110217.07