Name
Title | ||
|---|---|---|
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs |
Abstract | ||
|---|---|---|
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to speedup performance. Many such circuits have been previously designed for acceleration via application-specific integrated circuits (ASICs). Redesigning an ASIC circuit for FPGA implementation involves several challenges. We describe a case study that highlights a common challenge related to memories. The study involves converting a pattern counting circuit architecture, based on a pipelined binary tree and originally designed for ASIC implementation, into a circuit suitable for FPGAs. The original ASIC-oriented circuit, when mapped to a Spartan 3e FPGA, could process 10 million patterns per second and handle up to 4,096 patterns. The redesigned circuit could instead process 100 million patterns per second and handle up to 32,768 patterns, representing a 10x performance improvement and a 4x utilization improvement. The redesign involved partitioning large memories into smaller ones at the expense of redundant control logic. Through this and other case studies, design patterns may emerge that aid designers in redesigning ASIC circuits for FPGAs as well as in building new high-performance and efficient circuits for FPGAs. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1450135.1450171 | CODES+ISSS |
Keywords | Field | DocType |
original asic-oriented circuit,efficient circuit,application-specific integrated circuit,asic circuit,asic implementation,circuit architecture,redesigning asic circuit,million pattern,case study,fpga implementation,field programmable gate array,design pattern,design patterns,stream,embedded computing,asic,fpga,high throughput,binary tree,memory,application specific integrated circuit | Computer science,Software design pattern,Real-time computing,Integrated circuit,Speedup,Computer architecture,Parallel computing,Field-programmable gate array,Application-specific integrated circuit,Control logic,Electronic circuit,Reconfigurable computing,Embedded system | Conference |
Citations | PageRank | References |
6 | 0.48 | 14 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Sheldon | 1 | 56 | 5.42 |
| Frank Vahid | 2 | 2688 | 218.00 |