| An Analysis of Using Many Small Programs in CS1 | 1 | 0.35 | 2019 |
| Python Versus C++: An Analysis of Student Struggle on Small Coding Exercises in Introductory Programming Courses. | 2 | 0.40 | 2018 |
| Teaching Students a Systematic Approach to Debugging: (Abstract Only). | 0 | 0.34 | 2018 |
| Students learn more with less text that covers the same core topics | 3 | 0.82 | 2015 |
| Interactive Ebooks and Course Materials: A BOF for Authors and Instructors (Abstract Only) | 0 | 0.34 | 2015 |
| Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation | 1 | 0.35 | 2015 |
| A Survey on Concepts, Applications, and Challenges in Cyber-Physical Systems. | 20 | 0.90 | 2014 |
| Accurate and Efficient Algorithms that Adapt to Privacy-Enhanced Video for Improved Assistive Monitoring | 2 | 0.39 | 2013 |
| An efficient compression scheme for checkpointing of FPGA-based digital mockups | 0 | 0.34 | 2013 |
| Estimating Daily Energy Expenditure from Video for Assistive Monitoring | 4 | 0.43 | 2013 |
| Exploration with upgradeable models using statistical methods for physical model emulation | 0 | 0.34 | 2013 |
| An online revolution in learning and teaching | 1 | 0.43 | 2013 |
| Automatic synthesis of physical system differential equation models to a custom network of general processing elements on FPGAs | 4 | 0.47 | 2013 |
| Combining code reordering and cache configuration | 2 | 0.36 | 2012 |
| MNFL: the monitoring and notification flow language for assistive monitoring | 1 | 0.36 | 2012 |
| MEDS: mockup electronic data sheets for automated testing of cyber-physical systems using digital mockups | 0 | 0.34 | 2012 |
| Synthesis of custom networks of heterogeneous processing elements for complex physical system emulation | 3 | 0.39 | 2012 |
| Privacy perception and fall detection accuracy for in-home video assistive monitoring with privacy enhancements | 10 | 0.90 | 2012 |
| Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators | 4 | 0.41 | 2011 |
| Scalable object detection accelerators on FPGAs using custom design space exploration | 5 | 0.53 | 2011 |
| Making good points: application-specific pareto-point generation for design space exploration using statistical methods | 7 | 0.49 | 2009 |
| Portable SystemC-on-a-chip | 5 | 0.49 | 2009 |
| Enabling nonexpert construction of basic sensor-based systems | 11 | 0.63 | 2009 |
| Design and implementation of a MicroBlaze-based warp processor | 24 | 1.12 | 2009 |
| Transmuting coprocessors: Dynamic loading of FPGA coprocessors | 10 | 0.56 | 2009 |
| A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design | 0 | 0.34 | 2008 |
| Dynamic tuning of configurable architectures: the AWW online algorithm | 3 | 0.38 | 2008 |
| Warp Processing: Dynamic Translation of Binaries to FPGA Circuits | 21 | 1.67 | 2008 |
| Dynamic coprocessor management for FPGA-enhanced compute platforms | 15 | 0.76 | 2008 |
| Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs | 6 | 0.48 | 2008 |
| Highly-cited ideas in system codesign and synthesis | 0 | 0.34 | 2008 |
| Dynamic Partial Fpga Reconfiguration In A Prototype Microprocessor System | 5 | 0.49 | 2007 |
| Two-Level Microprocessor-Accelerator Partitioning | 7 | 0.52 | 2007 |
| Interactive presentation: Soft-core processor customization using the design of experiments paradigm | 7 | 0.86 | 2007 |
| A Self-Tuning Configurable Cache | 49 | 1.83 | 2007 |
| Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip | 4 | 0.56 | 2007 |
| Binary synthesis | 8 | 1.31 | 2007 |
| Automated generation of basic custom sensor-based embedded computing systems guided by end-user optimization criteria | 2 | 0.38 | 2006 |
| Configurable cache subsetting for fast cache tuning | 13 | 0.60 | 2006 |
| Warp Processors | 28 | 1.20 | 2006 |
| Conjoining soft-core FPGA processors | 7 | 0.90 | 2006 |
| A first look at the interplay of code reordering and configurable caches | 7 | 0.65 | 2005 |
| A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning | 43 | 2.18 | 2005 |
| eBlocks: an enabling technology for basic sensor based systems | 5 | 0.61 | 2005 |
| Fast Configurable-Cache Tuning With a Unified Second-Level Cache | 52 | 2.13 | 2005 |
| A logic block enabling logic configuration by non-experts in sensor networks | 10 | 0.82 | 2005 |
| New decompilation techniques for binary-level co-processor generation | 11 | 1.19 | 2005 |
| Techniques for synthesizing binaries to an advanced register/memory structure | 15 | 0.84 | 2005 |
| System synthesis for networks of programmable blocks | 6 | 0.53 | 2005 |
| A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning | 34 | 1.52 | 2004 |
