Name
Abstract | ||
|---|---|---|
Growing number of excessively long on-chip wires in modern monolithic ICs is a byproduct of growing chip size. To address this problem instead of placing all systems components in one layer (i.e. in 2-D space) one can use a stack of single layer monolithic ICs (called here a 2.5-D integrated IC). To assess the potential benefits of such a 2.5-D integration schema this paper compares wire length distributions, obtained for 2-D and 2.5-D implementations of benchmark circuits. In the assessment two newly developed floorplanning and placement tools were used. Significant reductions in both total wirelength and worst-case wirelength was observed for the systems implemented as 2.5-D ICs. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1145/369691.369763 | ISPD |
Keywords | Field | DocType |
placement,wirelength,systems component,worst-case wirelength,floorplanning,single layer,chip size,total wirelength,partition,modern monolithic ics,benchmark circuit,integrated ic,bounded sliceline grid,2.5-d system integration,monolithic ics,vlsi,2-d space,system integration scheme,system integration,chip | Computer science,Parallel computing,Implementation,Chip size,Electronic circuit,Interconnection,Very-large-scale integration,System integration,Floorplan | Conference |
ISBN | Citations | PageRank |
1-58113-347-2 | 80 | 5.94 |
References | Authors | |
4 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yangdong Deng | 1 | 429 | 44.78 |
| Wojciech Maly | 2 | 1976 | 352.57 |