Paper Info
Title
A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays
Abstract
Computation of peak supply current is central to power rail design and analysis of power supply switching noise. Traditionally, peak switching current from all CMOS gates is added together to compute peak supply current. This approach can be improved significantly if temporal and Boolean relationships are taken into consideration. Previously, it was shown that worst case switching current in a subset of gates may imply that some other gates may not have the worst case switching condition due to logical relationship between input patterns of a gate. In this paper, we also take integer gate delays into consideration to show that gate switching events may be spaced out in time leading to lower peak current. Further, it is found that taking gate delays into account actually simplifies the size of individual problem instances to be solved, leading to both a faster and more accurate solution. Finally, we compare peak current waveform generated by the proposed solver against SPICE simulation to demonstrate effectiveness of the proposed solution.
Year
DOI
Venue
2012
10.1109/TC.2011.128
IEEE Trans. Computers
Keywords
Field
DocType
cmos gate,gate delays,pattern generation technique,power supply,switching supply,gate delay,power rail design,proposed solution,peak supply current,accurate solution,worst case,peak current waveform,integer gate delay,vlsi,logic gate,cmos integrated circuits,switches,integrated circuit,logic gates,automatic test pattern generation
Automatic test pattern generation,Logic gate,Spice,Computer science,Waveform,Real-time computing,CMOS,Solver,Very-large-scale integration,Computation
Journal
Volume
Issue
ISSN
61
7
0018-9340
Citations 
PageRank 
References 
1
0.38
21
Authors
3
Name
Order
Citations
PageRank
Kunal Ganeshpure1273.45
Alodeep Sanyal2598.66
Sandip Kundu31103137.18