Name
Abstract | ||
|---|---|---|
Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90 nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45 nm node. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1687399.1687496 | ICCAD |
Keywords | Field | DocType |
mobility,compact stress model,layout dependence,carrier transport properties,cmos integrated circuits,design optimization,carrier mobility enhancement,new layout-dependent stress model,pattern decomposition,integrated circuit modelling,circuit layout,stress modeling,sti stress effect,tcad simulation,cmos design,circuit analysis,layout decomposition,non-uniform stress distribution,technology cad (electronics),efficient model extraction,strain technology,cmos fabrication,integrated circuit design,layout-dependent stress model,stress effect,circuit performance,threshold voltage shift,process technology,layout-dependent stress effect,circuit simulation,carrier mobility,first principle,threshold voltage,modeling and simulation,stress,effective stress,transistors,silicon,layout,mathematical model | Computer science,Modeling and simulation,Circuit extraction,Electronic engineering,CMOS,Integrated circuit design,Network analysis,Physical design,Transistor,Threshold voltage | Conference |
ISSN | ISBN | Citations |
1092-3152 | 978-1-60558-800-1 | 8 |
PageRank | References | Authors |
1.07 | 5 | 5 |