Paper Info
Title
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology
Abstract
This paper presents a scan chain design for dual-rail asynchronous circuits. This is a true asynchronous scan chain because no clock is needed even in scan mode. This is a full-scan design for testability (DfT) so only combinational automatic test pattern generation (ATPG) is needed and the fault coverage of generated test patterns is very high. This technique can be applied to various kinds of asynchronous circuits, including pipelines, state machines, and interconnects. Experiments on an 8051 datapath circuit show that the coverage is as high as 99.59%. This technique has been proven to work successfully in 8 μm Thin-film transistor (TFT) technology on the glass.
Year
DOI
Venue
2011
10.1007/s10836-011-5195-x
J. Electronic Testing
Keywords
Field
DocType
Asynchronous circuits,Scan chains,Thin film transistor,Design for testability
Design for testing,Asynchronous communication,Automatic test pattern generation,Asynchronous system,Fault coverage,Computer science,Scan chain,Electronic engineering,Real-time computing,Transistor,Test compression
Journal
Volume
Issue
ISSN
27
2
0923-8174
Citations 
PageRank 
References 
2
0.37
20
Authors
2
Name
Order
Citations
PageRank
Chi-Hsuan Cheng120.37
James Chien-Mo Li218727.16