Title
Efficient tree topology for FPGA interconnect network
Abstract
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butter y-Fat-Tree topology, and an upward network using hierarchy. Studies based on Rent's Rule show that switch requirements in this architecture grow slower than in traditional Mesh topologies. New tools are developed to place and route several benchmark circuits on this architecture. Experimental results show that the Tree-based architecture can implement MCNC benchmark circuits with an average gain of 54% in total area compared with Mesh architecture.
Year
DOI
Venue
2008
10.1145/1366110.1366186
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
place and route
Architecture,Computer science,Parallel computing,Field-programmable gate array,Place and route,Network topology,Real-time computing,Electronic engineering,Rent's rule,Hierarchy,Electronic circuit,Interconnection
Conference
Citations 
PageRank 
References 
11
0.65
11
Authors
4
Name
Order
Citations
PageRank
Zied Marrakchi115228.68
Hayder Mrabet2847.44
Emna Amouri3397.83
Habib Mehrez420039.21