Title
Shared-port register file architecture for low-energy VLIW processors
Abstract
We propose a reduced-port Register File (RF) architecture for reducing RF energy in a VLIW processor. With port reduction, RF ports need to be shared among Function Units (FUs), which may lead to access conflicts, and thus, reduced performance. Our solution includes (i) a carefully designed RF-FU interconnection network that permits port sharing with minimum conflicts and without any delay/energy overheads, and (ii) a novel scheduling and binding algorithm that reduces the performance penalty. With our solution, we observed as much as 83% RF energy savings with no more than a 10% loss in performance for a set of Mediabench and Mibench benchmarks.
Year
DOI
Venue
2014
10.1145/2533397
TACO
Keywords
Field
DocType
port reduction,rf port,rf energy,reduced performance,energy overhead,shared-port register file architecture,port sharing,performance penalty,low-energy vliw processor,function units,rf energy saving,mibench benchmarks
Port (computer networking),Architecture,Very long instruction word,Scheduling (computing),Computer science,Parallel computing,Register file,Real-time computing,Radio frequency,Interconnection,Overhead (business)
Journal
Volume
Issue
ISSN
11
1
1544-3566
Citations 
PageRank 
References 
4
0.40
30
Authors
3
Name
Order
Citations
PageRank
Neeraj Goel150.77
Anshul Kumar239948.45
Preeti Ranjan Panda378689.40