Paper Info
Title
Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches
Abstract
Multi-core chips have been increasingly adopted by the microprocessor industry. For real-time systems to exploit multi-core architectures, it is required to obtain both tight and safe estimates of worst-case execution times (WCETs). Estimating WCETs for multi-core platforms is very challenging because of the possible interferences between cores due to shared hardware resources such as shared caches, memory bus, etc. This paper proposes a compile-time approach to reduce shared instruction cache interferences between cores to tighten WCET estimations. Unlike [YAN08], which accounts for all possible conflicts caused by tasks running on the other cores when estimating the WCET of a task, our approach drastically reduces the amount of inter-core interferences. This is done by controlling the contents of the shared instruction cache(s), by caching only blocks statically known as reused. Experimental results demonstrate the practicality of our approach.
Year
DOI
Venue
2009
10.1109/RTSS.2009.34
Washington, DC
Keywords
Field
DocType
possible conflict,tighten wcet estimates,shared instruction caches,compile-time approach,multi-core processors,multi-core architecture,wcet estimation,estimating wcets,shared cache,multi-core platform,shared hardware resource,instruction cache interference,shared instruction cache,multi core processor,cache memory,real time systems,computer architecture,multicore processors,estimation,multi core processors,frequency modulation,worst case execution time,data mining,static analysis,chip
Cache,Computer science,Parallel computing,Static analysis,Microprocessor,Exploit,Real-time computing,Memory bus,Multi-core processor,Embedded system
Conference
ISSN
ISBN
Citations 
1052-8725
978-0-7695-3875-4
44
PageRank 
References 
Authors
1.86
25
3
Name
Order
Citations
PageRank
Damien Hardy116110.07
Thomas Piquet2863.47
Isabelle Puaut3170889.84