Paper Info
Title
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction
Abstract
7 Gb/s/pin operation without bank group restriction in a GDDR5 SDRAM is achieved by skewed control logic and current-mode I/O sense amplifiers with regular calibration from replica impedance monitors. The bank-to-bank active time is shortened to 2.5 ns by a FIFO-based BLSA enabler, 2.0 ns latency VPP generator and active jitter canceler. The chip is fabricated in a 50 nm DRAM process in a 61.6 mm2 die area.
Year
DOI
Venue
2010
10.1109/ISSCC.2010.5433889
ISSCC
Keywords
DocType
ISSN
calibration,time 2.5 ns,time 2 ns,vpp generator,fifo-based blsa enabler,amplifiers,jitter,no bank-group restriction,gddr5 sdram,skewed control logic,dram chips,regular calibration,current-mode i/o sense amplifiers,active jitter canceler,size 50 nm,replica impedance monitors,bank-to-bank active time,current-mode circuits,generators
Conference
0193-6530
ISBN
Citations 
PageRank 
978-1-4244-6033-5
3
0.68
References 
Authors
0
30
Name
Order
Citations
PageRank
Tae-young Oh1568.23
Young-Soo Sohn211521.21
Seung-Jun Bae316732.40
Min-Sang Park46613.05
Ji-Hoon Lim530.68
Yong-Ki Cho6314.66
Dae-Hyun Kim73214.38
Dong-Min Kim813015.54
Hye-Ran Kim9489.04
Hyun-Joong Kim1030.68
Jin Hyun Kim119221.61
Jin-Kook Kim12456.80
Young-Sik Kim1339454.26
Byeong-Cheol Kim14325.48
Sang-Hyup Kwak15314.66
Jaehyung Lee1613616.13
Jaeyoung Lee17454102.07
Chang-Ho Shin18456.84
Yun-Seok Yang19314.66
Beom-Sig Cho20223.31
Sam-Young Bang216313.01
Hyang-Ja Yang22396.60
Young-Ryeol Choi23416.46
Gil-Shin Moon246111.93
Cheol-Goo Park25396.60
Seokwon Hwang268114.51
Jeong-Don Lim27314.66
Kwang-Il Park2816325.68
Joo-Sun Choi2924629.16
Young-Hyun Jun306815.92