| Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond | 2 | 0.40 | 2021 |
| A Methodology Combining Cosine Similarity with Classifier for Text Classification | 2 | 0.37 | 2020 |
| A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques | 1 | 0.37 | 2020 |
| A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration | 0 | 0.34 | 2019 |
| An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM | 0 | 0.34 | 2018 |
| Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM. | 1 | 0.37 | 2018 |
| Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices | 8 | 0.42 | 2017 |
| 18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution. | 1 | 0.48 | 2016 |
| Poster: SoEasy - A Software Framework for Easy Peripheral Control Programming in Diverse Hardware Platforms. | 0 | 0.34 | 2016 |
| Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM | 3 | 0.36 | 2015 |
| A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation | 9 | 1.09 | 2015 |
| 25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation | 13 | 1.36 | 2014 |
| Hmm And Rule-Based Hybrid Intruder Detection Approach By Synthesizing Decisions Of Sensors | 0 | 0.34 | 2013 |
| A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface | 20 | 1.29 | 2012 |
| A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction | 19 | 2.63 | 2011 |
| A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW | 9 | 1.35 | 2011 |
| Correction on “A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme” [Aug 09 2222-2232] | 0 | 0.34 | 2010 |
| A Crosstalk-And-Isi Equalizing Receiver In 2-Drop Single-Ended Sstl Memory Channel | 6 | 0.68 | 2010 |
| A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction | 3 | 0.68 | 2010 |
| A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces. | 7 | 0.78 | 2009 |
| A 0.13- m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN | 1 | 0.37 | 2009 |
| A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces | 7 | 0.65 | 2009 |
| Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation | 2 | 0.50 | 2009 |
| An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion | 22 | 5.33 | 2008 |
| A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques. | 8 | 1.94 | 2008 |
| A DLL with Jitter-Reduction Techniques for DRAM Interfaces | 2 | 0.51 | 2007 |
| A Wormhole Router with Embedded Broadcasting Virtual Bus for Mesh Computers | 2 | 0.39 | 2000 |
| A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting | 2 | 0.38 | 1999 |
| MetaCore: an application specific DSP development system | 13 | 1.29 | 1998 |
