Name
Title | ||
|---|---|---|
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique |
Abstract | ||
|---|---|---|
A 9-bit 80 MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low power and a small area, is presented. The 9-bit capacitor array consists of only 16 unit capacitors and a coupling capacitor due to the proposed binary-weighted split-capacitor arrays with a merged-capacitor switching technique. The proposed ADC includes a comparator with offset cancellation and uses digital calibration for error correction. The ADC is implemented in a 65-nm complimentary metal-oxide-semiconductor technology and occupies an active area of 0.068 mm2 with a reference buffer. The differential and integral nonlinearities of the ADC are less than 0.37 and 0.40 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 50.71 dB, a spurious-free dynamic range of 66.72 dB, and an effective number of bits of 8.13 bits with a 78 MHz sinusoidal input at 80 MS/s. The ADC consumes 3.4 mW with the reference buffer at a 1.0-V supply and achieves a figure of merit of 78 fJ/conversion step. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCSII.2010.2048387 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
small area,error correction,successive approximation register (sar) analog-to-digital converter (adc),analogue-digital conversion,complimentary metal-oxide-semiconductor technology,adc consumes,size 65 nm,proposed binary-weighted split-capacitor array,binary-weighted split-capacitor arrays,frequency 78 mhz,digital calibration,successive approximation register analog-to-digital converter,unit capacitor,offset cancellation,merged-capacitor switching technique,integral nonlinearity,9-bit capacitor array,proposed adc,reference buffer,capacitors,voltage 1 v,coupling capacitor,cmos digital integrated circuits,merged-capacitor switching (mcs),power 3.4 mw,successive approximation register analog-to-digital,differential nonlinearity,comparator,capacitor reduction technique,split-capacitor array,active area,65-nm complimentary metal-oxide-semiconductor technology,signal-to-noise-distortion ratio,calibration,spurious free dynamic range,dynamic range,figure of merit,switches,cmos technology,capacitance,effective number of bits | Integral nonlinearity,Comparator,Capacitor,Differential nonlinearity,Control theory,Analog-to-digital converter,Electronic engineering,Effective number of bits,Figure of merit,Successive approximation ADC,Electrical engineering,Mathematics | Journal |
Volume | Issue | ISSN |
57 | 7 | 1549-7747 |
Citations | PageRank | References |
16 | 1.92 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Young-Kyun Cho | 1 | 19 | 5.05 |
| Young-Deuk Jeon | 2 | 98 | 13.50 |
| Jae-Won Nam | 3 | 29 | 6.41 |
| Jong-Kee Kwon | 4 | 158 | 23.10 |