Name
Abstract | ||
|---|---|---|
A Built-In Self-Test (BIST) methodology and a test pattern generation (TPG) architecture for testing static random access memory (SRAM) interconnect at board level via IEEE 1149.1 Boundary Scan (BS) Architecture are presented. Due to the expense and complexity of BS circuitry the widely-used SRAMs on most modern telecommunication circuit boards seldom contain BS architecture. (We call such non-boundary scan ICs cluster-ICs.) Hence, a methodology that tests the large numbers of board-level interconnects at the control, address, and data lines of cluster SRAMs is necessary. This is especially essential for board-level interconnect BIST which is used not only for manufacturing testing but also for system testing after integration. Newly identified prohibited conditions, which enable re-arrangement and merger of tests, are incorporated into test conditions for SRAM cluster interconnects. These improvements have been exploited to develop an efficient test procedure that is suitable for BIST. The proposed BIST methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable SRAM cluster interconnect faults, (iii) have low area overhead, and (iv) have short test lengths |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ATS.2000.893603 | Asian Test Symposium |
Keywords | Field | DocType |
testable sram cluster interconnect fault detection,printed circuit testing,integrated circuit interconnections,bs architecture,test condition,bs circuitry,short test length,test pattern generation architecture,sram chips,sram cluster interconnect testing,automatic test pattern generation,board-level interconnects,sram cluster interconnects,boundary scan testing,static random access memory,built-in self test,cluster srams,ieee 1149.1 boundary scan architecture,test pattern generation,bist tpg,system testing,board level,prohibited conditions,proposed bist methodology,logic testing,efficient test procedure,printed circuits | Boundary scan,Automatic test pattern generation,System testing,Computer science,Manufacturing testing,Electronic engineering,Static random-access memory,Interconnection,Built-in self-test,Telecommunication circuit,Embedded system | Conference |
ISSN | ISBN | Citations |
1081-7735 | 0-7695-0887-1 | 1 |
PageRank | References | Authors |
0.49 | 5 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chen-Huan Chiang | 1 | 53 | 7.33 |
| S. K. Gupta | 2 | 1 | 0.82 |