Name
Abstract | ||
|---|---|---|
Two fast algorithms for static test sequencecompaction are proposed for sequential circuits.The algorithms are based on the observation thattest sequences traverse through a small set ofstates, and some states are frequently re-visitedthroughout the application of a test set. Subsequencesthat start and end on the same states maybe removed if necessary and sufficient conditionsare met for them. The techniques require onlytwo fault simulation passes and are applied to testsequences... |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/VTEST.1997.600260 | IEEE VLSI Test Symposium |
Keywords | Field | DocType |
static compaction,various test generator,static test sequence compaction,sequential circuit,significant compaction,small set,test set,sequential circuit test vectors,revisited state,fast algorithm,test sequences traverse,fast algorithms,fault simulation pass,sequential circuits,vlsi | Stuck-at fault,Automatic test pattern generation,Sequential logic,Fault coverage,Computer science,Algorithm,Real-time computing,Electronic engineering,Test compression,Very-large-scale integration,Traverse,Test set | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-8186-7810-0 | 24 |
PageRank | References | Authors |
1.95 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael S. Hsiao | 1 | 1467 | 132.13 |
| Elizabeth M. Rudnick | 2 | 867 | 76.37 |
| J. H. Patel | 3 | 4577 | 527.59 |