Name
Abstract | ||
|---|---|---|
This paper presents an efficient method to block unknown values from entering temporal compactors. The control signals for the blocking logic are generated by an LFSR. The proposed technique minimizes the size of the LFSR by propagating only one fault effect for each fault and balancing the number of specified bits in each control pattern. The linear solver to find seeds of the LFSR intelligently chooses a solution such that the impact on test quality is minimal. Experimental results show that sizes of control data for the proposed method are smaller than prior work and run time of the proposed method is several orders of magnitude smaller than that of prior work. Hardware overhead is very low. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/DATE.2006.243929 | DATE |
Keywords | Field | DocType |
control data,hardware overhead,control signal,control pattern,fault effect,proposed technique,efficient method,prior work,efficient unknown,lfsr reseeding,compaction,shift registers,automatic test equipment,logic design,logic gates,linear feedback shift register,testing,hardware,logic circuits,signal generators,observability,value engineering,xml | Logic synthesis,Orders of magnitude (numbers),Logic gate,Observability,Shift register,Automatic test equipment,Computer science,Parallel computing,Signal generator,Real-time computing,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1530-1591 | 3-9810801-0-6 | 2 |
PageRank | References | Authors |
0.41 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seongmoon Wang | 1 | 605 | 48.50 |
| Kedarnath J. Balakrishnan | 2 | 160 | 10.85 |
| Srimat T. Chakradhar | 3 | 2492 | 185.94 |