Title
A real-time motion estimation FPGA architecture
Abstract
A motion estimation architecture allowing the execution of a variety of block-matching search techniques is presented in this paper. The ability to choose the most efficient search technique with respect to speeding up the process and locating the best matching target block leads to the improvement of the quality of service and the performance of the video encoding. The proposed architecture is pipelined to efficiently support a large set of currently used block-matching algorithms including Diamond Search, 3-step, MVFAST and PMVFAST. The proposed design executes the algorithms by providing a set of instructions common for all the block-matching algorithms and a few instructions accommodating the specific actions of each technique. Moreover, the architecture supports the use of different search techniques at the block level. The results and performance measurements of the architecture have been validated on FPGA supporting maximum throughput of 30 frames/s with frame size 1,024 × 768.
Year
DOI
Venue
2008
10.1007/s11554-007-0070-9
J. Real-Time Image Processing
Keywords
DocType
Volume
fpgavideo encodingmotion estimation � real timeblock-matching,real time,block matching algorithm,quality of service,motion estimation
Journal
3
Issue
ISSN
Citations 
1-2
1861-8219
11
PageRank 
References 
Authors
0.66
18
8